{"id":1206,"date":"2025-09-27T18:36:42","date_gmt":"2025-09-27T10:36:42","guid":{"rendered":"https:\/\/ulpcb.com\/?page_id=1206"},"modified":"2025-09-28T20:41:25","modified_gmt":"2025-09-28T12:41:25","slug":"32-layer-ic-test-pcb-2","status":"publish","type":"page","link":"https:\/\/ulpcb.com\/ja\/32-layer-ic-test-pcb-2\/","title":{"rendered":"32 layer IC test PCB"},"content":{"rendered":"<div data-elementor-type=\"wp-page\" data-elementor-id=\"1206\" class=\"elementor elementor-1206\">\n\t\t\t\t<div class=\"wd-negative-gap elementor-element elementor-element-41fb3de0 e-flex e-con-boxed e-con e-parent\" data-id=\"41fb3de0\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-22b7c60a wd-el-breadcrumbs text-left elementor-widget elementor-widget-wd_element_breadcrumbs\" data-id=\"22b7c60a\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"wd_element_breadcrumbs.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<nav class=\"wd-breadcrumbs\"><a href=\"https:\/\/ulpcb.com\/ja\/\">Home<\/a><span class=\"wd-delimiter\"><\/span><span class=\"wd-last\">\u56fa\u5b9a\u30da\u30fc\u30b8<\/span><\/nav>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"wd-negative-gap elementor-element elementor-element-329654ba e-flex e-con-boxed e-con e-parent\" data-id=\"329654ba\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t<div class=\"elementor-element elementor-element-29dc062 e-con-full e-flex e-con e-child\" data-id=\"29dc062\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t<div class=\"elementor-element elementor-element-7e008e91 wd-width-100 elementor-widget elementor-widget-wd_images_gallery\" data-id=\"7e008e91\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"wd_images_gallery.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"wd-images-gallery photoswipe-images wd-carousel-container\" style=\"--wd-align-items:center; --wd-justify-content:center;\">\n\t\t\t\t\t\t\t<div class=\"wd-carousel-inner\">\n\t\t\t\t\t\t<div class=\"wd-carousel wd-grid\" data-wrap=\"yes\" style=\"--wd-col-lg:1;--wd-col-md:1;--wd-col-sm:1;--wd-gap-lg:0px;\">\n\t\t\t\t\t\t\t\t\t<div class=\"wd-carousel-wrap\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<div class=\"wd-gallery-item wd-carousel-item\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<a  href=\"https:\/\/ulpcb.com\/wp-content\/uploads\/2025\/09\/32-layer-IC-test-pcb.webp\" data-width=\"495\" data-height=\"375\" data-index=\"1\" data-elementor-open-lightbox=\"no\">\n\t\t\t\t\t\t\n\t\t\t\t\t\t<img fetchpriority=\"high\" decoding=\"async\" width=\"495\" height=\"375\" src=\"https:\/\/ulpcb.com\/wp-content\/uploads\/2025\/09\/32-layer-IC-test-pcb.webp\" class=\"attachment-600x400 size-600x400\" alt=\"The 32 - layer IC test PCB board is the core carrier for high - end integrated circuit testing. It focuses on high - density interconnection and high - precision signal transmission. It uses an alternating lamination of &quot;signal layer - ground layer - power layer&quot;, contains multiple independent test loops, and supports synchronous testing of 32 or more ICs\" srcset=\"https:\/\/ulpcb.com\/wp-content\/uploads\/2025\/09\/32-layer-IC-test-pcb.webp 495w, https:\/\/ulpcb.com\/wp-content\/uploads\/2025\/09\/32-layer-IC-test-pcb-300x227.webp 300w, https:\/\/ulpcb.com\/wp-content\/uploads\/2025\/09\/32-layer-IC-test-pcb-16x12.webp 16w\" sizes=\"(max-width: 495px) 100vw, 495px\" \/>\n\t\t\t\t\t\t\t\t\t\t\t\t\t<\/a>\n\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t<div class=\"wd-nav-arrows wd-pos-sep wd-hover-1 wd-icon-1\">\n\t\t\t<div class=\"wd-btn-arrow wd-prev wd-disabled\">\n\t\t\t\t<div class=\"wd-arrow-inner\"><\/div>\n\t\t\t<\/div>\n\t\t\t<div class=\"wd-btn-arrow wd-next\">\n\t\t\t\t<div class=\"wd-arrow-inner\"><\/div>\n\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\n\t\t\t\t<\/div>\n\n\t\t\t\t\t\t<div class=\"wd-nav-pagin-wrap text-center wd-style-shape wd-hide-md-sm wd-hide-sm\">\n\t\t\t<ul class=\"wd-nav-pagin\"><\/ul>\n\t\t<\/div>\n\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-1b98c774 e-con-full e-flex e-con e-child\" data-id=\"1b98c774\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t<div class=\"elementor-element elementor-element-49aaa91b elementor-widget elementor-widget-heading\" data-id=\"49aaa91b\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t\t<h1 class=\"elementor-heading-title elementor-size-default\">32 layer IC test pcb<\/h1>\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-6a4e11e6 elementor-widget elementor-widget-wd_text_block\" data-id=\"6a4e11e6\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"wd_text_block.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"wd-text-block reset-last-child text-left\">\n\t\t\t\n\t\t\t<h2>The 32 - layer IC test PCB board serves as the core for high - end integrated circuit testing, emphasizing high - density interconnection and high - precision signal transmission. With an alternating lamination of \"signal layer - ground layer - power layer\", it has multiple independent test loops, enabling synchronous testing of 32 or more ICs. The board integrates micro - probe interfaces and impedance - matching networks (50\u03a9\/75\u03a9), suitable for the function, timing, and performance tests of complex ICs like CPUs and FPGAs. High - Tg FR - 4 base materials (Tg\u2265180\u2103) are selected. By passing strict signal integrity tests, it ensures accurate test data, catering to semiconductor R &amp; D and mass - production quality inspection processes.<\/h2>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-5271c8d1 e-con-full e-flex e-con e-child\" data-id=\"5271c8d1\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t<div class=\"elementor-element elementor-element-6f459f86 elementor-widget elementor-widget-wd_popup\" data-id=\"6f459f86\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"wd_popup.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<div class=\"wd-button-wrapper text-left\" >\n\t\t\t<a class=\"btn btn-style-default btn-shape-rectangle btn-size-default wd-open-popup btn-color-primary btn-icon-pos-right\"  href=\"#quote\">\n\t\t\t\t<span class=\"wd-btn-text\" data-elementor-setting-key=\"text\">\n\t\t\t\t\tGet a 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M\u1edf m\u1ee5c b\u1eb1ng ph\u00edm Enter ho\u1eb7c Space, \u0111\u00f3ng b\u1eb1ng ph\u00edm Esc v\u00e0 di chuy\u1ec3n b\u1eb1ng c\u00e1c ph\u00edm m\u0169i t\u00ean.\" data-no-translation-aria-label=\"\">\n\t\t\t<div class=\"e-n-tabs-heading\" role=\"tablist\">\n\t\t\t\t\t<button id=\"e-n-tab-title-3714568121\" data-tab-title-id=\"e-n-tab-title-3714568121\" class=\"e-n-tab-title\" aria-selected=\"true\" data-tab-index=\"1\" role=\"tab\" tabindex=\"0\" aria-controls=\"e-n-tab-content-3714568121\" style=\"--n-tabs-title-order: 1;\">\n\t\t\t\t\t\t<span class=\"e-n-tab-title-text\">\n\t\t\t\tDescription\t\t\t<\/span>\n\t\t<\/button>\n\t\t\t\t\t<\/div>\n\t\t\t<div class=\"e-n-tabs-content\">\n\t\t\t\t<div id=\"e-n-tab-content-3714568121\" role=\"tabpanel\" aria-labelledby=\"e-n-tab-title-3714568121\" data-tab-index=\"1\" style=\"--n-tabs-title-order: 1;\" class=\"e-active elementor-element elementor-element-752bd00b e-con-full e-flex e-con e-child\" data-id=\"752bd00b\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t<div class=\"wd-negative-gap elementor-element elementor-element-541f0bcb e-flex e-con-boxed e-con e-child\" data-id=\"541f0bcb\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-5b51772d elementor-widget elementor-widget-wd_text_block\" data-id=\"5b51772d\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"wd_text_block.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"wd-text-block reset-last-child text-left\">\n\t\t\t\n\t\t\t<h3 class=\"header-vfC6AV auto-hide-last-sibling-br\">I. Base - material Pretreatment: Guarantee for High - frequency and Low - loss<\/h3><div class=\"auto-hide-last-sibling-br paragraph-JOTKXA paragraph-element br-paragraph-space\">Modified FR - 4 base materials with a high Tg (\u2265180\u2103) and low loss (Df\u22640.002@10GHz) are selected. The dielectric constant is controlled at 3.8\u00b10.2 to ensure stable high - frequency signal transmission. In the pretreatment stage:<\/div><div class=\"container-utlnW2 md-box-line-break wrapper-d0Cc1k undefined\">\u00a0<\/div><ul class=\"auto-hide-last-sibling-br\"><li>After CNC cutting (with an accuracy of \u00b10.05mm), perform plasma cleaning (in an oxygen atmosphere, with a power of 800W for 3min) to remove surface organic impurities.<\/li><li>Bake in a vacuum at 120\u2103 for 4h to control the water content of the base material below 0.02%, avoiding bubbles in subsequent lamination.<\/li><li>Select electrolytic copper for the copper foil (with a thickness of 12\u03bcm) with a surface roughness Ra\u22640.3\u03bcm to reduce high - frequency signal transmission losses.<\/li><\/ul><h3 class=\"header-vfC6AV auto-hide-last-sibling-br\">II. Inner - layer Fabrication: Ultra - fine Circuit Formation Technology<\/h3><div class=\"auto-hide-last-sibling-br paragraph-JOTKXA paragraph-element br-paragraph-space\">For the 32 - layer board, 16 groups of inner - layer core boards need to be fabricated first. The core process focuses on the precision control of ultra - fine circuits:<\/div><div class=\"container-utlnW2 md-box-line-break wrapper-d0Cc1k undefined\">\u00a0<\/div><ul class=\"auto-hide-last-sibling-br\"><li>Choose a 5\u03bcm ultra - thin photosensitive film for the dry - film. Use electrostatic adsorption + hot - pressing (60\u2103, 0.3kg\/cm\u00b2) for lamination to ensure no bubbles.<\/li><li>Use LDI laser exposure (with a wavelength of 355nm and a positioning accuracy of \u00b12\u03bcm). The edge roughness of the 30\u03bcm line - width \/ 30\u03bcm line - spacing pattern should be \u22643\u03bcm.<\/li><li>After alkaline development (1.0% sodium carbonate, 28\u2103), adopt a micro - etching process (ammonium persulfate solution, with an etching amount of 0.5\u03bcm) to avoid under - etching.<\/li><li>The AOI inspection is equipped with a 5\u03bcm resolution camera to identify open - circuits, short - circuits, and line - width deviations (a deviation exceeding \u00b13\u03bcm is judged as a defect).<\/li><li>The blackening treatment uses a nano - level oxidation process to form a 0.1\u03bcm thick oxide layer, with an inter - layer peel strength of \u22651.8N\/mm.<\/li><\/ul><h3 class=\"header-vfC6AV auto-hide-last-sibling-br\">III. Lamination Integration: Precise Interconnection of 32 Layers<\/h3><div class=\"auto-hide-last-sibling-br paragraph-JOTKXA paragraph-element br-paragraph-space\">Lamination is the core link determining the performance of the 32 - layer board. It needs to solve the problems of multi - layer alignment and resin filling:<\/div><div class=\"container-utlnW2 md-box-line-break wrapper-d0Cc1k undefined\">\u00a0<\/div><ul class=\"auto-hide-last-sibling-br\"><li>The lamination adopts a \"signal - ground - power\" symmetrical structure. Three groups of optical positioning targets with a diameter of 0.1mm are set on each layer.<\/li><li>In a vacuum laminator, the CCD vision system is used to achieve precise alignment of 16 groups of core boards, with a cumulative error of \u226415\u03bcm.<\/li><li>Select a low - flow prepreg (PP) (with a fluidity of 10 - 15%), a dielectric constant of 4.0\u00b10.1, and a thickness deviation of \u22645\u03bcm.<\/li><li>The stepped lamination curve: 60\u2103\/10min (pre - heating) \u2192 120\u2103\/30min (10kg\/cm\u00b2, resin flowing) \u2192 180\u2103\/90min (30kg\/cm\u00b2, curing), with a cooling rate of \u22642\u2103\/min.<\/li><li>After lamination, use X - Ray to detect inter - layer misalignment. The deviation of each layer should be \u22645\u03bcm; otherwise, it will be scrapped.<\/li><\/ul><h3 class=\"header-vfC6AV auto-hide-last-sibling-br\">IV. Drilling and Via Metallization: Guarantee for Micro - interconnection Reliability<\/h3><div class=\"auto-hide-last-sibling-br paragraph-JOTKXA paragraph-element br-paragraph-space\">The 32 - layer board contains a large number of blind and buried holes (with a diameter of 50 - 100\u03bcm). Via metallization needs to break through the problem of the depth - diameter ratio:<\/div><div class=\"container-utlnW2 md-box-line-break wrapper-d0Cc1k undefined\">\u00a0<\/div><ul class=\"auto-hide-last-sibling-br\"><li>Use laser drilling (a UV laser with a wavelength of 355nm) to process blind holes. The hole - wall roughness Ra\u22641\u03bcm, and the hole - diameter deviation is \u00b15\u03bcm.<\/li><li>Use mechanical drilling (a tungsten - steel drill bit with a diameter of 0.15 - 0.3mm) to process through - holes, with a rotation speed of 120000rpm and a feed of 0.5m\/min.<\/li><li>Hole - wall treatment: Plasma desmear (a CF4\/O2 mixed gas for 5min) \u2192 micro - etching (a sulfuric acid \/ hydrogen peroxide system, with an etching amount of 1\u03bcm).<\/li><li>Electroless copper plating (with a palladium catalyst, a copper - plating thickness of 0.5\u03bcm) \u2192 electro - plating copper (with a current density of 1A\/dm\u00b2, a hole - copper thickness of \u226520\u03bcm), ensuring a hole resistance of \u22642m\u03a9.<\/li><li>Use hole - wall integrity inspection (metallographic sectioning + SEM scanning) to ensure no voids, pinholes, etc.<\/li><\/ul><h3 class=\"header-vfC6AV auto-hide-last-sibling-br\">V. Outer - layer Processing: Optimization of High - frequency Signal Performance<\/h3><div class=\"auto-hide-last-sibling-br paragraph-JOTKXA paragraph-element br-paragraph-space\">The outer - layer needs to achieve precise impedance control of 50\u03a9\/75\u03a9. The key process points are:<\/div><div class=\"container-utlnW2 md-box-line-break wrapper-d0Cc1k undefined\">\u00a0<\/div><ul class=\"auto-hide-last-sibling-br\"><li>The outer - layer circuit adopts the semi - additive process (SAP): Thin the copper foil (etch to 5\u03bcm) \u2192 tin - plating pattern \u2192 copper - plating (30\u03bcm line - width) \u2192 remove tin, with a line - width accuracy of \u00b12\u03bcm.<\/li><li>Impedance adjustment: By controlling the thickness of the dielectric layer (with an error of \u00b13\u03bcm) and the copper thickness (with an error of \u00b11\u03bcm), control the impedance error within \u00b15%.<\/li><li>Use photosensitive low - loss solder - mask ink (Df\u22640.003) with a thickness of 10 - 15\u03bcm, and use laser to open windows (with an accuracy of \u00b15\u03bcm).<\/li><li>Surface treatment: Use electroless gold - plating for the test pads (with a gold thickness of 0.8 - 1.2\u03bcm and a nickel thickness of 5 - 8\u03bcm), with a contact resistance of \u226410m\u03a9.<\/li><li>Cut the shape with a laser (with an accuracy of \u00b110\u03bcm), and the edge burrs should be \u22642\u03bcm to avoid signal - transmission interference.<\/li><\/ul><h3 class=\"header-vfC6AV auto-hide-last-sibling-br\">VI. Finished - product Inspection: Comprehensive Performance Verification<\/h3><div class=\"auto-hide-last-sibling-br paragraph-JOTKXA paragraph-element br-paragraph-space\">The 32 - layer IC test board needs to pass strict inspections to ensure test accuracy:<\/div><div class=\"container-utlnW2 md-box-line-break wrapper-d0Cc1k undefined\">\u00a0<\/div><ul class=\"auto-hide-last-sibling-br\"><li><strong>Electrical Performance<\/strong>: Use a flying - probe test (with an accuracy of \u00b11\u03bcm) to detect open - circuits and short - circuits. Use a TDR time - domain reflectometer to measure impedance (50\u03a9\/75\u03a9).<\/li><li><strong>Signal Integrity<\/strong>: Use a vector network analyzer to test the insertion loss (\u22641dB@20GHz) and return loss (\u226515dB@20GHz).<\/li><li><strong>Environmental Reliability<\/strong>: After 1000 thermal shock cycles from - 55\u2103 to 125\u2103, the impedance change rate should be \u22645%.<\/li><li><strong>Microscopic Inspection<\/strong>: Randomly select 5% of the products for metallographic sectioning to observe the inter - layer bonding and hole - wall conditions.<\/li><li><strong>Function Testing<\/strong>: Mount a standard IC for 32 - channel synchronous testing, with a data consistency error of \u22640.1%.<\/li><\/ul><div class=\"container-utlnW2 md-box-line-break wrapper-d0Cc1k undefined\">\u00a0<\/div><div class=\"auto-hide-last-sibling-br paragraph-JOTKXA paragraph-element br-paragraph-space\">The process flow of the 32 - layer IC test PCB board achieves the core characteristics of \"high - density, high - precision, and high - stability\" through the fine - tuned control of 128 processes. It provides a reliable carrier for the R &amp; D testing and mass - production quality inspection of 7nm and below advanced - process ICs, promoting the continuous upgrade of semiconductor industry testing technology<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-3e281d0b elementor-widget elementor-widget-wd_image_or_svg\" data-id=\"3e281d0b\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"wd_image_or_svg.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\n\t\t<div class=\"wd-image text-left\">\n\t\t\t\t\t\t\t\t<img decoding=\"async\" width=\"495\" height=\"375\" src=\"https:\/\/ulpcb.com\/wp-content\/uploads\/2025\/09\/32-layer-IC-test-pcb.webp\" class=\"attachment-full size-full\" alt=\"The 32 - layer IC test PCB board is the core carrier for high - end integrated circuit testing. It focuses on high - density interconnection and high - precision signal transmission. It uses an alternating lamination of &quot;signal layer - ground layer - power layer&quot;, contains multiple independent test loops, and supports synchronous testing of 32 or more ICs\" srcset=\"https:\/\/ulpcb.com\/wp-content\/uploads\/2025\/09\/32-layer-IC-test-pcb.webp 495w, https:\/\/ulpcb.com\/wp-content\/uploads\/2025\/09\/32-layer-IC-test-pcb-300x227.webp 300w, https:\/\/ulpcb.com\/wp-content\/uploads\/2025\/09\/32-layer-IC-test-pcb-16x12.webp 16w\" sizes=\"(max-width: 495px) 100vw, 495px\" \/>\t\t\t\t\t<\/div>\n\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>","protected":false},"excerpt":{"rendered":"<p>Home\u9875\u9762 32 layer IC test pcb The 32 &#8211; layer IC test PCB board serves as the core for high<\/p>","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-1206","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/ulpcb.com\/ja\/wp-json\/wp\/v2\/pages\/1206","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ulpcb.com\/ja\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/ulpcb.com\/ja\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/ulpcb.com\/ja\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/ulpcb.com\/ja\/wp-json\/wp\/v2\/comments?post=1206"}],"version-history":[{"count":4,"href":"https:\/\/ulpcb.com\/ja\/wp-json\/wp\/v2\/pages\/1206\/revisions"}],"predecessor-version":[{"id":1414,"href":"https:\/\/ulpcb.com\/ja\/wp-json\/wp\/v2\/pages\/1206\/revisions\/1414"}],"wp:attachment":[{"href":"https:\/\/ulpcb.com\/ja\/wp-json\/wp\/v2\/media?parent=1206"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}