{"id":35,"date":"2025-08-17T10:21:01","date_gmt":"2025-08-17T02:21:01","guid":{"rendered":"https:\/\/ulpcb.com\/?page_id=35"},"modified":"2025-09-28T00:24:40","modified_gmt":"2025-09-27T16:24:40","slug":"multi-layer-pcb","status":"publish","type":"page","link":"https:\/\/ulpcb.com\/as\/pcb-product\/multi-layer-pcb\/","title":{"rendered":"Multi-layer PCB"},"content":{"rendered":"<div data-elementor-type=\"wp-page\" data-elementor-id=\"35\" class=\"elementor elementor-35\">\n\t\t\t\t<div class=\"wd-negative-gap elementor-element elementor-element-c2906a6 e-flex e-con-boxed e-con e-parent\" data-id=\"c2906a6\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-8e0f4b9 wd-el-breadcrumbs text-left elementor-widget elementor-widget-wd_element_breadcrumbs\" data-id=\"8e0f4b9\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"wd_element_breadcrumbs.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<nav class=\"wd-breadcrumbs\"><a href=\"https:\/\/ulpcb.com\/as\/\">Home<\/a><span class=\"wd-delimiter\"><\/span><span class=\"wd-last\">\u09aa\u09c3\u09b7\u09cd\u09a0\u09be <\/span><\/nav>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"wd-negative-gap elementor-element elementor-element-c95e5a9 e-flex e-con-boxed e-con e-parent\" data-id=\"c95e5a9\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t<div class=\"elementor-element elementor-element-a41b7bf e-con-full e-flex e-con e-child\" data-id=\"a41b7bf\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t<div class=\"elementor-element elementor-element-a45a24d wd-width-100 elementor-widget elementor-widget-wd_images_gallery\" data-id=\"a45a24d\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"wd_images_gallery.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"wd-images-gallery photoswipe-images wd-carousel-container\" style=\"--wd-align-items:center; --wd-justify-content:center;\">\n\t\t\t\t\t\t\t<div class=\"wd-carousel-inner\">\n\t\t\t\t\t\t<div class=\"wd-carousel wd-grid\" data-wrap=\"yes\" style=\"--wd-col-lg:1;--wd-col-md:1;--wd-col-sm:1;--wd-gap-lg:0px;\">\n\t\t\t\t\t\t\t\t\t<div class=\"wd-carousel-wrap\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<div class=\"wd-gallery-item wd-carousel-item\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<a  href=\"https:\/\/ulpcb.com\/wp-content\/uploads\/2025\/09\/242-HDI.webp\" data-width=\"569\" data-height=\"427\" data-index=\"1\" data-elementor-open-lightbox=\"no\">\n\t\t\t\t\t\t\n\t\t\t\t\t\t<img fetchpriority=\"high\" decoding=\"async\" width=\"533\" height=\"400\" src=\"https:\/\/ulpcb.com\/wp-content\/uploads\/2025\/09\/242-HDI.webp\" class=\"attachment-600x400 size-600x400\" alt=\"HDI is the abbreviation of High Density Interconnector. As electronic products tend to be more multi - functional and complex, the contact distances of integrated circuit components are reduced, and the signal transmission speed is increased. This requires the application of high - density circuit configuration and micro - via technology, thus giving rise to HDI boards.\" srcset=\"https:\/\/ulpcb.com\/wp-content\/uploads\/2025\/09\/242-HDI.webp 569w, https:\/\/ulpcb.com\/wp-content\/uploads\/2025\/09\/242-HDI-300x225.webp 300w, https:\/\/ulpcb.com\/wp-content\/uploads\/2025\/09\/242-HDI-16x12.webp 16w\" sizes=\"(max-width: 533px) 100vw, 533px\" \/>\n\t\t\t\t\t\t\t\t\t\t\t\t\t<\/a>\n\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t<div class=\"wd-nav-arrows wd-pos-sep wd-hover-1 wd-icon-1\">\n\t\t\t<div class=\"wd-btn-arrow wd-prev wd-disabled\">\n\t\t\t\t<div class=\"wd-arrow-inner\"><\/div>\n\t\t\t<\/div>\n\t\t\t<div class=\"wd-btn-arrow wd-next\">\n\t\t\t\t<div class=\"wd-arrow-inner\"><\/div>\n\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\n\t\t\t\t<\/div>\n\n\t\t\t\t\t\t<div class=\"wd-nav-pagin-wrap text-center wd-style-shape wd-hide-md-sm wd-hide-sm\">\n\t\t\t<ul class=\"wd-nav-pagin\"><\/ul>\n\t\t<\/div>\n\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-7705963 e-con-full e-flex e-con e-child\" data-id=\"7705963\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t<div class=\"elementor-element elementor-element-ced8203 elementor-widget elementor-widget-heading\" data-id=\"ced8203\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t\t<h1 class=\"elementor-heading-title elementor-size-default\">Multi-layer PCB<\/h1>\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-1e4aa7a elementor-widget elementor-widget-wd_text_block\" data-id=\"1e4aa7a\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"wd_text_block.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"wd-text-block reset-last-child text-left\">\n\t\t\t\n\t\t\t<h2 class=\"auto-hide-last-sibling-br paragraph-JOTKXA paragraph-element br-paragraph-space\">Mainly high - Tg FR - 4 is used, with Tg (glass - transition temperature) \u2265 170\u2103, dielectric constant (Dk) of 4.0 - 4.7, dielectric loss (Df) \u2264 0.02. It has a moderate cost and mature processing, suitable for mobile phone motherboards, routers, etc. In some high - temperature scenarios (such as automotive electronics), ultra - high Tg FR - 4 (Tg\u2265200\u2103) is selected to improve temperature - resistance stability.For high - frequency scenarios (5G base stations, radars): PTFE (Polytetrafluoroethylene) or BT resin base materials are adopted. PTFE has a Dk as low as 2.0 - 2.2 and Df \u2264 0.001, suitable for 77GHz millimeter - wave radars. BT resin has a Dk of 3.0 - 3.5, heat - resistance above 260\u2103, and its cost is only 60% of that of PTFE, suitable for mobile phone RF modules.<\/h2>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-e86649c e-con-full e-flex e-con e-child\" data-id=\"e86649c\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t<div class=\"elementor-element elementor-element-b03ab91 elementor-widget elementor-widget-wd_popup\" data-id=\"b03ab91\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"wd_popup.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<div class=\"wd-button-wrapper text-left\" >\n\t\t\t<a class=\"btn btn-style-default btn-shape-rectangle btn-size-default wd-open-popup btn-color-primary btn-icon-pos-right\"  href=\"#quote\">\n\t\t\t\t<span class=\"wd-btn-text\" data-elementor-setting-key=\"text\">\n\t\t\t\t\tGet a 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400V214.398c22.914 18.251 55.409 43.862 104.938 82.646 21.857 17.205 60.134 55.186 103.062 54.955 42.717.231 80.509-37.199 103.053-54.947 49.528-38.783 82.032-64.401 104.947-82.653V400H48z\"><\/path><\/svg>\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t<\/a>\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-e735afa elementor-widget-divider--view-line elementor-widget elementor-widget-divider\" data-id=\"e735afa\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"divider.default\">\n\t\t\t\t\t\t\t<div class=\"elementor-divider\">\n\t\t\t<span class=\"elementor-divider-separator\">\n\t\t\t\t\t\t<\/span>\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"wd-negative-gap elementor-element elementor-element-9c1533a e-flex e-con-boxed e-con e-parent\" data-id=\"9c1533a\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t\t<div 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class=\"e-n-tab-title-text\">\n\t\t\t\tDescription\t\t\t<\/span>\n\t\t<\/button>\n\t\t\t\t\t<\/div>\n\t\t\t<div class=\"e-n-tabs-content\">\n\t\t\t\t<div id=\"e-n-tab-content-2030956781\" role=\"tabpanel\" aria-labelledby=\"e-n-tab-title-2030956781\" data-tab-index=\"1\" style=\"--n-tabs-title-order: 1;\" class=\"e-active elementor-element elementor-element-c13f473 e-con-full e-flex e-con e-child\" data-id=\"c13f473\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t<div class=\"wd-negative-gap elementor-element elementor-element-083ed12 e-flex e-con-boxed e-con e-child\" data-id=\"083ed12\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-597d555 elementor-widget elementor-widget-wd_text_block\" data-id=\"597d555\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"wd_text_block.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"wd-text-block reset-last-child text-left\">\n\t\t\t\n\t\t\t<h3 class=\"header-vfC6AV auto-hide-last-sibling-br\">I. Core Process of Manufacturing 4 - 10 - layer PCBs (Taking an 8 - layer FR - 4 Board as an Example)<\/h3><div class=\"auto-hide-last-sibling-br paragraph-JOTKXA paragraph-element br-paragraph-space\">The manufacturing of 4 - 10 - layer PCBs needs to strengthen \"inter - layer alignment\" and \"via metallization reliability\" based on conventional multi - layer boards. The full - process cycle is about 8 - 12 days. The core procedures can be divided into 6 major stages with 15 key operations:<div class=\"container-utlnW2 md-box-line-break wrapper-d0Cc1k undefined\">\u00a0<\/div><strong>Stage 1: Base - material Preparation and Design Conversion (Procedures 1 - 2)<\/strong><\/div><div class=\"container-utlnW2 md-box-line-break wrapper-d0Cc1k undefined\">\u00a0<\/div><ol class=\"auto-hide-last-sibling-br\"><li><strong>Base - material Selection and Cutting<\/strong><ul class=\"auto-hide-last-sibling-br\"><li><strong>Operation Details<\/strong>: Select high - Tg FR - 4 base materials (Tg\u2265170\u2103, core - board thickness of 0.2 - 0.4mm for 4 - layer boards and 0.1 - 0.2mm for 10 - layer boards), paired with 1OZ (35\u03bcm) electrolytic copper foil (for signal layers) or 2OZ (70\u03bcm) thick copper foil (for power\/ground layers). Cut them into a standard size of 500mm\u00d7600mm using a CNC cutting machine, with an error controlled within \u00b10.1mm. After cutting, remove surface oil stains by ultrasonic cleaning (40\u2103 neutral cleaning agent, for 15 minutes).<\/li><li><strong>Adaptation Differences<\/strong>: Due to the multiple layers in 10 - layer boards, base materials with low CTE (Z - direction \u2264 35ppm\/\u2103) should be selected to avoid warping after lamination.<\/li><\/ul><\/li><li><strong>CAM File Processing and Film Making<\/strong><ul class=\"auto-hide-last-sibling-br\"><li><strong>Operation Details<\/strong>: Import the Gerber design file into CAM software to generate films for inner layers (4 - 6 layers), outer - layer circuits, and the solder - mask layer. Mark the positions of blind holes (such as 1 - 2 layers \/ 7 - 8 layers blind holes in an 8 - layer board) and buried holes (3 - 6 layers buried holes). The films are made using a laser phototypesetter with a line - width accuracy of \u00b12\u03bcm. The optical density test should meet the requirements: \u22640.15 in the light - transmitting area and \u22654.0 in the light - blocking area.<div class=\"container-utlnW2 md-box-line-break wrapper-d0Cc1k undefined\">\u00a0<\/div><strong>Stage 2: Inner - layer Circuit Manufacturing (Procedures 3 - 5)<\/strong><\/li><\/ul><\/li><li><strong>Photosensitive Film Coating and Exposure<\/strong><ul class=\"auto-hide-last-sibling-br\"><li><strong>Operation Details<\/strong>: Roll - coat a photosensitive film (thickness of 15 - 20\u03bcm) on the surface of the inner - layer substrate and pre - bake at 60\u2103 for 30 minutes. Use LDI (Laser - Direct Imaging) to replace traditional film exposure, with a positioning accuracy of \u00b11\u03bcm and an exposure energy of 80 - 100mJ\/cm\u00b2 to form the circuit pattern. For 10 - layer boards, additional \"alignment targets\" should be added to the inner layers to ensure subsequent lamination alignment.<\/li><\/ul><\/li><li><strong>Development and Etching<\/strong><ul class=\"auto-hide-last-sibling-br\"><li><strong>Operation Details<\/strong>: Develop with a 1.0 - 1.2% sodium carbonate solution (35\u2103) for 3 - 5 minutes to remove the uncured photosensitive film. Etch with an acidic copper chloride etchant (concentration of 180g\/L, 45\u2103) at an etching rate of 1.2\u03bcm\/min. Offset the under - etching by \"etching compensation\" (increasing the designed line - width by 8 - 10\u03bcm) to ensure the final line - width deviation is \u2264\u00b13\u03bcm. After etching, strip the film with a 5% sodium hydroxide solution.<\/li><\/ul><\/li><li><strong>Inner - layer AOI Inspection<\/strong><ul class=\"auto-hide-last-sibling-br\"><li><strong>Key Control<\/strong>: Use an Automated Optical Inspection (AOI) device to compare the circuits with the design pattern and detect defects such as open - circuits (area \u2265 0.01mm\u00b2), short - circuits (spacing \u2264 0.05mm), and abnormal line - widths. 10 - layer boards need to be fully inspected at 100%, and the sampling inspection ratio for 4 - layer boards should be \u226530%. Defective boards need to be marked for rework, and the rework rate should be \u22642%.<div class=\"container-utlnW2 md-box-line-break wrapper-d0Cc1k undefined\">\u00a0<\/div><strong>Stage 3: Lamination and Stacking (Procedures 6 - 7)<\/strong><\/li><\/ul><\/li><li><strong>Stacking Assembly and Pre - alignment<\/strong><ul class=\"auto-hide-last-sibling-br\"><li><strong>Operation Details<\/strong>: Stack in the order of \"outer copper foil\u2192prepreg\u2192inner layer 1\u2192prepreg\u2192inner layer 2\u2192\u2026\u2192inner layer n\u2192prepreg\u2192outer copper foil\" (for an 8 - layer board: outer copper foil\u21921080 prepreg \u00d72\u2192inner layer 1\u2192106 prepreg \u00d71\u2192inner layer 2\u2192106 prepreg \u00d71\u2192inner layer 3\u2192106 prepreg \u00d71\u2192inner layer 4\u21921080 prepreg \u00d72\u2192outer copper foil). Align the reference holes through a CCD optical positioning system, with a positioning deviation of \u2264\u00b12\u03bcm. After stacking, fix with rivets to prevent displacement.<\/li><li><strong>Material Adaptation<\/strong>: The resin content of the prepreg should match the number of layers (50 - 55% for 4 - layer boards and 55 - 60% for 10 - layer boards) to avoid delamination due to insufficient resin flow.<\/li><\/ul><\/li><li><strong>Vacuum Lamination<\/strong><ul class=\"auto-hide-last-sibling-br\"><li><strong>Operation Details<\/strong>: Send the stacked body to a vacuum laminator and execute a step - by - step temperature - control program:<ul class=\"auto-hide-last-sibling-br\"><li><strong>Exhaust Stage<\/strong>: At 80\u2103, 10kg\/cm\u00b2 for 30 minutes (vacuum degree \u2264 10mbar).<\/li><li><strong>Resin - flow Stage<\/strong>: 150\u2103, 25kg\/cm\u00b2 for 40 minutes.<\/li><li><strong>Curing Stage<\/strong>: 180\u2103, 30kg\/cm\u00b2 for 60 - 90 minutes (extended by 30 minutes for 10 - layer boards).<\/li><\/ul><\/li><li><strong>Key Monitoring<\/strong>: Monitor the temperature uniformity (\u00b13\u2103) in real - time during lamination to avoid local overheating causing resin carbonization.<div class=\"container-utlnW2 md-box-line-break wrapper-d0Cc1k undefined\">\u00a0<\/div><strong>Stage 4: Drilling and Via Metallization (Procedures 8 - 10)<\/strong><\/li><\/ul><\/li><li><strong>Positioning Drilling<\/strong><ul class=\"auto-hide-last-sibling-br\"><li><strong>Operation Details<\/strong>: Use an X - ray drilling machine to position the inner - layer reference holes and process through - holes (aperture of 0.3 - 0.5mm), blind holes (0.15 - 0.2mm), and buried holes (0.2 - 0.3mm). For 10 - layer boards, the blind - hole process adopts a \"laser pre - drilling + mechanical fine - drilling\" composite process. The laser power is 5W (355nm UV laser), the mechanical drill rotation speed is 80000r\/min, and the feed rate is 5mm\/min. After drilling, blow out the residue in the holes with 0.5MPa compressed air to avoid hole blockage.<\/li><\/ul><\/li><li><strong>Desmear and Electroless Copper Plating<\/strong><ul class=\"auto-hide-last-sibling-br\"><li><strong>Operation Details<\/strong>: Immerse in an alkaline potassium permanganate solution (70 - 80\u2103) for 5 - 8 minutes to remove the resin residue and carbonized layer on the hole wall. Immerse in an electroless copper - plating solution (copper sulfate concentration of 15g\/L, 25\u2103) for 15 minutes to deposit a 0.8 - 1\u03bcm thin copper layer on the hole wall to ensure hole - wall conductivity. After copper - plating, test the hole resistance (\u226450m\u03a9), and the non - qualification rate should be \u22640.5%.<\/li><\/ul><\/li><li><strong>Electro - plating Thickening<\/strong><ul class=\"auto-hide-last-sibling-br\"><li><strong>Operation Details<\/strong>: Use a vertical electro - plating process with a current density of 1 - 1.5A\/dm\u00b2 and an electro - plating time of 60 - 90 minutes to thicken the copper layer on the hole wall to 20 - 25\u03bcm and the outer copper foil to 50\u03bcm. For 10 - layer boards, electro - plate in segments (first plate the holes, then the surface) to avoid a hole - copper thickness difference exceeding 30% due to uneven current distribution. After electro - plating, rinse with deionized water to prevent the remaining plating solution from corroding the copper layer.<div class=\"container-utlnW2 md-box-line-break wrapper-d0Cc1k undefined\">\u00a0<\/div><strong>Stage 5: Outer - layer Processing (Procedures 11 - 13)<\/strong><\/li><\/ul><\/li><li><strong>Outer - layer Circuit Manufacturing<\/strong><ul class=\"auto-hide-last-sibling-br\"><li><strong>Operation Details<\/strong>: Repeat the inner - layer process of \"photosensitive film coating - LDI exposure - development - etching\". The outer - layer circuits need to be precisely connected to the blind holes\/buried holes, with an alignment deviation of \u2264\u00b13\u03bcm. After etching, conduct a second AOI inspection, focusing on checking the connection integrity between the outer - layer circuits and the holes to avoid the \"no - copper - in - hole\" defect.<\/li><\/ul><\/li><li><strong>Solder - mask Layer Printing and Curing<\/strong><ul class=\"auto-hide-last-sibling-br\"><li><strong>Operation Details<\/strong>: Screen - print photosensitive solder - mask ink (thickness of 20 - 30\u03bcm, mainly green). For 10 - layer boards, print twice (the first time to fill and level the holes, the second time to cover the whole board). After UV exposure (energy of 1500mJ\/cm\u00b2), cure at 150\u2103 for 60 minutes to ensure the ink adhesion is \u22655B (cross - cut test). The solder - mask opening size should be 0.1 - 0.2mm larger than the pads to avoid covering the pads.<\/li><\/ul><\/li><li><strong>Surface Treatment and Shape Processing<\/strong><ul class=\"auto-hide-last-sibling-br\"><li><strong>Operation Details<\/strong>: Treat the pad areas with gold - plating (2 - 5\u03bcm gold layer, 5 - 10\u03bcm nickel layer) or OSP (thickness of 0.5 - 1\u03bcm). Cut the shape with a CNC milling machine, with an error of \u2264\u00b10.1mm. For 10 - layer boards, use \"fixture fixation + step - by - step cutting\" to avoid inter - layer delamination caused by vibration. After cutting, grind the edges to remove burrs (\u22643\u03bcm).<div class=\"container-utlnW2 md-box-line-break wrapper-d0Cc1k undefined\">\u00a0<\/div><strong>Stage 6: Finished - product Inspection and Delivery (Procedures 14 - 15)<\/strong><\/li><\/ul><\/li><li><strong>Comprehensive Performance Testing<\/strong><ul class=\"auto-hide-last-sibling-br\"><li><strong>Electrical Performance<\/strong>: Use a flying - probe tester to detect open - circuits and short - circuits (insulation resistance \u2265 10\u00b9\u2070\u03a9, withstand voltage of 1000V\/1 minute without breakdown), and impedance (50\u03a9 single - end impedance deviation \u2264 \u00b15%).<\/li><li><strong>Physical Performance<\/strong>: Use a laser thickness gauge to detect the board thickness (thickness difference on the same board \u2264 0.05mm), and conduct \u91d1\u76f8\u5207\u7247 (metallographic sectioning) to analyze the inter - layer bonding (no bubbles, no delamination).<\/li><li><strong>Reliability Testing<\/strong>: Sample for temperature cycling (-40\u2103~125\u2103, 1000 times) and damp - heat testing (85\u2103\/85% RH, 1000h), with no performance degradation after testing.<\/li><\/ul><\/li><li><strong>Packaging and Delivery<\/strong><ul class=\"auto-hide-last-sibling-br\"><li><strong>Operation Details<\/strong>: Pack qualified products in anti - static bags, place desiccants (moisture content \u2264 20%) in each bag. Stack 4 - layer boards for packaging (height \u2264 10cm), and use layered trays for 10 - layer boards to avoid extrusion deformation. Attach a test report when delivering, including electrical performance data and reliability test results to ensure traceability.<\/li><\/ul><\/li><\/ol><h3 class=\"header-vfC6AV auto-hide-last-sibling-br\">II. Core Quality Management System (QMS) for 4 - 10 - layer PCBs<\/h3><ol class=\"auto-hide-last-sibling-br\"><li><strong>Incoming Quality Control (IQC): Controlling Material Quality at the Source<\/strong><ul class=\"auto-hide-last-sibling-br\"><li><strong>Base - material Testing<\/strong>: Randomly inspect 5 sheets per batch. Test Tg (by Differential Scanning Calorimetry DSC), dielectric constant (by impedance analyzer), and water absorption rate (by 120\u2103 baking weight - loss method). Reject the entire batch if it is unqualified.<\/li><li><strong>Copper Foil\/Prepreg Testing<\/strong>: Test the roughness (Ra\u22640.8\u03bcm) and tensile strength (\u2265300MPa) of the copper foil, and test the resin content (error \u00b12%) and resin - flow amount (20 - 30%) of the prepreg to ensure they match the base material.<\/li><\/ul><\/li><li><strong>In - process Quality Control (IPQC): Real - time Monitoring of Key Processes<\/strong><ul class=\"auto-hide-last-sibling-br\"><li><strong>Inner - layer Etching<\/strong>: Randomly inspect 1 board every 30 minutes. Measure the line - width with a microscope (deviation \u2264 \u00b13\u03bcm), and test the etchant concentration once an hour (copper chloride concentration of 180\u00b15g\/L).<\/li><li><strong>Lamination Process<\/strong>: Monitor the temperature (\u00b13\u2103), pressure (\u00b11kg\/cm\u00b2), and vacuum degree (\u226410mbar) in real - time. After laminating the first piece, conduct \u91d1\u76f8\u5207\u7247 (metallographic sectioning) to confirm no bubbles between layers (bubbles with a diameter \u2264 50\u03bcm are unqualified).<\/li><li><strong>Via Metallization<\/strong>: Test the hole resistance (\u226450m\u03a9) every hour after copper - plating, and test the hole - copper thickness (20 - 25\u03bcm) after electro - plating. Adjust the plating solution parameters immediately if the values exceed the tolerance.<\/li><\/ul><\/li><li><strong>Final Quality Control\/Final Quality Inspection (FQC\/OQC): Verifying All Items for Qualified Delivery<\/strong><ul class=\"auto-hide-last-sibling-br\"><li><strong>FQC Full - inspection<\/strong>: Inspect the appearance (no bubbles or exposed copper in the solder - mask layer, no oxidation on the pads) and dimensions (shape error \u2264 \u00b10.1mm) at 100%. The sampling inspection ratio for electrical performance should be \u226510%.<\/li><li><strong>OQC Sampling Inspection<\/strong>: Randomly inspect 3% of each batch for reliability testing (temperature cycling, damp - heat), and check the consistency between the test report and the product to ensure no mis - dispatch or missed inspection.<\/li><\/ul><\/li><li><strong>Abnormality Control: Closing - loop Handling of Quality Issues<\/strong><ul class=\"auto-hide-last-sibling-br\"><li><strong>Abnormality Response<\/strong>: If non - conformity (such as inner - layer short - circuit) is found during the process, stop the machine immediately. The QE (Quality Engineer) analyzes the cause (such as deviation in exposure parameters, etchant contamination) and formulates corrective measures (adjust exposure energy, replace the etchant).<\/li><li><strong>Traceability System<\/strong>: Assign a unique SN code to each board, record the base - material batch, process parameters, and test results. If quality problems occur later, it can be traced back to the specific process and responsible person to avoid batch accidents.<\/li><\/ul><\/li><\/ol><h3 class=\"header-vfC6AV auto-hide-last-sibling-br\">III. Differential Adaptation of Manufacturing and Control for 4 - 10 - layer PCBs<\/h3><div class=\"auto-hide-last-sibling-br mdbox-table-root table-container-GhL7Lo\" data-scroll-inline-overflow=\"true\" data-scroll-inline-at-start=\"true\" data-scroll-inline-start-overflow=\"false\" data-scroll-inline-at-end=\"false\" data-scroll-inline-end-overflow=\"true\"><div class=\"table-scroll-container-hgHkfW mdbox-table-scroll-container\"><table><thead><tr><th>Number of Layers<\/th><th>Core Manufacturing Differences<\/th><th>Quality Control Focus<\/th><th>Typical Application Scenarios<\/th><\/tr><\/thead><tbody><tr><td>4 - layer<\/td><td>Simple stacking (2 inner layers + 2 outer layers), low lamination difficulty<\/td><td>Focus on inner - layer etching precision and via - metallization reliability for through - holes<\/td><td>Router motherboards, industrial control modules<\/td><\/tr><tr><td>6 - 8 - layer<\/td><td>Need to design buried holes (inner - layer interconnection), high lamination alignment requirements<\/td><td>Add inter - layer alignment detection (deviation \u2264 \u00b12\u03bcm) and buried - hole conductivity testing<\/td><td>Automotive central control systems, server power boards<\/td><\/tr><tr><td>10 - layer<\/td><td>Complex stacking (6 inner layers + 2 outer layers), need segmented electro - plating<\/td><td>Full - process AOI inspection, increase the sampling ratio of reliability testing to 5%<\/td><td>New - energy vehic<\/td><\/tr><\/tbody><\/table><\/div><\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-98291ab elementor-widget elementor-widget-wd_image_or_svg\" data-id=\"98291ab\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"wd_image_or_svg.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\n\t\t<div class=\"wd-image text-left\">\n\t\t\t\t\t\t\t\t<img decoding=\"async\" width=\"569\" height=\"427\" src=\"https:\/\/ulpcb.com\/wp-content\/uploads\/2025\/09\/242-HDI.webp\" class=\"attachment-full size-full\" alt=\"HDI is the abbreviation of High Density Interconnector. As electronic products tend to be more multi - functional and complex, the contact distances of integrated circuit components are reduced, and the signal transmission speed is increased. This requires the application of high - density circuit configuration and micro - via technology, thus giving rise to HDI boards.\" srcset=\"https:\/\/ulpcb.com\/wp-content\/uploads\/2025\/09\/242-HDI.webp 569w, https:\/\/ulpcb.com\/wp-content\/uploads\/2025\/09\/242-HDI-300x225.webp 300w, https:\/\/ulpcb.com\/wp-content\/uploads\/2025\/09\/242-HDI-16x12.webp 16w\" sizes=\"(max-width: 569px) 100vw, 569px\" \/>\t\t\t\t\t<\/div>\n\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>","protected":false},"excerpt":{"rendered":"<p>Home\u9875\u9762 Multi-layer PCB Mainly high &#8211; Tg FR &#8211; 4 is used, with Tg (glass &#8211; transition temperature) \u2265 170\u2103,<\/p>","protected":false},"author":1,"featured_media":0,"parent":15,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-35","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/ulpcb.com\/as\/wp-json\/wp\/v2\/pages\/35","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ulpcb.com\/as\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/ulpcb.com\/as\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/ulpcb.com\/as\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/ulpcb.com\/as\/wp-json\/wp\/v2\/comments?post=35"}],"version-history":[{"count":58,"href":"https:\/\/ulpcb.com\/as\/wp-json\/wp\/v2\/pages\/35\/revisions"}],"predecessor-version":[{"id":1258,"href":"https:\/\/ulpcb.com\/as\/wp-json\/wp\/v2\/pages\/35\/revisions\/1258"}],"up":[{"embeddable":true,"href":"https:\/\/ulpcb.com\/as\/wp-json\/wp\/v2\/pages\/15"}],"wp:attachment":[{"href":"https:\/\/ulpcb.com\/as\/wp-json\/wp\/v2\/media?parent=35"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}