Multi-layer PCB

I. Core Process of Manufacturing 4 - 10 - layer PCBs (Taking an 8 - layer FR - 4 Board as an Example)

1. Base - material Selection and Cutting
   • Operation Details: Select high - Tg FR - 4 base materials (Tg≥170℃, core - board thickness of 0.2 - 0.4mm for 4 - layer boards and 0.1 - 0.2mm for 10 - layer boards), paired with 1OZ (35μm) electrolytic copper foil (for signal layers) or 2OZ (70μm) thick copper foil (for power/ground layers). Cut them into a standard size of 500mm×600mm using a CNC cutting machine, with an error controlled within ±0.1mm. After cutting, remove surface oil stains by ultrasonic cleaning (40℃ neutral cleaning agent, for 15 minutes).
   • Adaptation Differences: Due to the multiple layers in 10 - layer boards, base materials with low CTE (Z - direction ≤ 35ppm/℃) should be selected to avoid warping after lamination.
2. CAM File Processing and Film Making
   • Operation Details: Import the Gerber design file into CAM software to generate films for inner layers (4 - 6 layers), outer - layer circuits, and the solder - mask layer. Mark the positions of blind holes (such as 1 - 2 layers / 7 - 8 layers blind holes in an 8 - layer board) and buried holes (3 - 6 layers buried holes). The films are made using a laser phototypesetter with a line - width accuracy of ±2μm. The optical density test should meet the requirements: ≤0.15 in the light - transmitting area and ≥4.0 in the light - blocking area.
      
     Stage 2: Inner - layer Circuit Manufacturing (Procedures 3 - 5)
3. Photosensitive Film Coating and Exposure
   • Operation Details: Roll - coat a photosensitive film (thickness of 15 - 20μm) on the surface of the inner - layer substrate and pre - bake at 60℃ for 30 minutes. Use LDI (Laser - Direct Imaging) to replace traditional film exposure, with a positioning accuracy of ±1μm and an exposure energy of 80 - 100mJ/cm² to form the circuit pattern. For 10 - layer boards, additional "alignment targets" should be added to the inner layers to ensure subsequent lamination alignment.
4. Development and Etching
   • Operation Details: Develop with a 1.0 - 1.2% sodium carbonate solution (35℃) for 3 - 5 minutes to remove the uncured photosensitive film. Etch with an acidic copper chloride etchant (concentration of 180g/L, 45℃) at an etching rate of 1.2μm/min. Offset the under - etching by "etching compensation" (increasing the designed line - width by 8 - 10μm) to ensure the final line - width deviation is ≤±3μm. After etching, strip the film with a 5% sodium hydroxide solution.
5. Inner - layer AOI Inspection
   • Key Control: Use an Automated Optical Inspection (AOI) device to compare the circuits with the design pattern and detect defects such as open - circuits (area ≥ 0.01mm²), short - circuits (spacing ≤ 0.05mm), and abnormal line - widths. 10 - layer boards need to be fully inspected at 100%, and the sampling inspection ratio for 4 - layer boards should be ≥30%. Defective boards need to be marked for rework, and the rework rate should be ≤2%.
      
     Stage 3: Lamination and Stacking (Procedures 6 - 7)
6. Stacking Assembly and Pre - alignment
   • Operation Details: Stack in the order of "outer copper foil→prepreg→inner layer 1→prepreg→inner layer 2→…→inner layer n→prepreg→outer copper foil" (for an 8 - layer board: outer copper foil→1080 prepreg ×2→inner layer 1→106 prepreg ×1→inner layer 2→106 prepreg ×1→inner layer 3→106 prepreg ×1→inner layer 4→1080 prepreg ×2→outer copper foil). Align the reference holes through a CCD optical positioning system, with a positioning deviation of ≤±2μm. After stacking, fix with rivets to prevent displacement.
   • Material Adaptation: The resin content of the prepreg should match the number of layers (50 - 55% for 4 - layer boards and 55 - 60% for 10 - layer boards) to avoid delamination due to insufficient resin flow.
7. Vacuum Lamination
   • Operation Details: Send the stacked body to a vacuum laminator and execute a step - by - step temperature - control program:
     • Exhaust Stage: At 80℃, 10kg/cm² for 30 minutes (vacuum degree ≤ 10mbar).
     • Resin - flow Stage: 150℃, 25kg/cm² for 40 minutes.
     • Curing Stage: 180℃, 30kg/cm² for 60 - 90 minutes (extended by 30 minutes for 10 - layer boards).
   • Key Monitoring: Monitor the temperature uniformity (±3℃) in real - time during lamination to avoid local overheating causing resin carbonization.
      
     Stage 4: Drilling and Via Metallization (Procedures 8 - 10)
8. Positioning Drilling
   • Operation Details: Use an X - ray drilling machine to position the inner - layer reference holes and process through - holes (aperture of 0.3 - 0.5mm), blind holes (0.15 - 0.2mm), and buried holes (0.2 - 0.3mm). For 10 - layer boards, the blind - hole process adopts a "laser pre - drilling + mechanical fine - drilling" composite process. The laser power is 5W (355nm UV laser), the mechanical drill rotation speed is 80000r/min, and the feed rate is 5mm/min. After drilling, blow out the residue in the holes with 0.5MPa compressed air to avoid hole blockage.
9. Desmear and Electroless Copper Plating
   • Operation Details: Immerse in an alkaline potassium permanganate solution (70 - 80℃) for 5 - 8 minutes to remove the resin residue and carbonized layer on the hole wall. Immerse in an electroless copper - plating solution (copper sulfate concentration of 15g/L, 25℃) for 15 minutes to deposit a 0.8 - 1μm thin copper layer on the hole wall to ensure hole - wall conductivity. After copper - plating, test the hole resistance (≤50mΩ), and the non - qualification rate should be ≤0.5%.
10. Electro - plating Thickening
    • Operation Details: Use a vertical electro - plating process with a current density of 1 - 1.5A/dm² and an electro - plating time of 60 - 90 minutes to thicken the copper layer on the hole wall to 20 - 25μm and the outer copper foil to 50μm. For 10 - layer boards, electro - plate in segments (first plate the holes, then the surface) to avoid a hole - copper thickness difference exceeding 30% due to uneven current distribution. After electro - plating, rinse with deionized water to prevent the remaining plating solution from corroding the copper layer.
       
      Stage 5: Outer - layer Processing (Procedures 11 - 13)
11. Outer - layer Circuit Manufacturing
    • Operation Details: Repeat the inner - layer process of "photosensitive film coating - LDI exposure - development - etching". The outer - layer circuits need to be precisely connected to the blind holes/buried holes, with an alignment deviation of ≤±3μm. After etching, conduct a second AOI inspection, focusing on checking the connection integrity between the outer - layer circuits and the holes to avoid the "no - copper - in - hole" defect.
12. Solder - mask Layer Printing and Curing
    • Operation Details: Screen - print photosensitive solder - mask ink (thickness of 20 - 30μm, mainly green). For 10 - layer boards, print twice (the first time to fill and level the holes, the second time to cover the whole board). After UV exposure (energy of 1500mJ/cm²), cure at 150℃ for 60 minutes to ensure the ink adhesion is ≥5B (cross - cut test). The solder - mask opening size should be 0.1 - 0.2mm larger than the pads to avoid covering the pads.
13. Surface Treatment and Shape Processing
    • Operation Details: Treat the pad areas with gold - plating (2 - 5μm gold layer, 5 - 10μm nickel layer) or OSP (thickness of 0.5 - 1μm). Cut the shape with a CNC milling machine, with an error of ≤±0.1mm. For 10 - layer boards, use "fixture fixation + step - by - step cutting" to avoid inter - layer delamination caused by vibration. After cutting, grind the edges to remove burrs (≤3μm).
       
      Stage 6: Finished - product Inspection and Delivery (Procedures 14 - 15)
14. Comprehensive Performance Testing
    • Electrical Performance: Use a flying - probe tester to detect open - circuits and short - circuits (insulation resistance ≥ 10¹⁰Ω, withstand voltage of 1000V/1 minute without breakdown), and impedance (50Ω single - end impedance deviation ≤ ±5%).
    • Physical Performance: Use a laser thickness gauge to detect the board thickness (thickness difference on the same board ≤ 0.05mm), and conduct 金相切片 (metallographic sectioning) to analyze the inter - layer bonding (no bubbles, no delamination).
    • Reliability Testing: Sample for temperature cycling (-40℃~125℃, 1000 times) and damp - heat testing (85℃/85% RH, 1000h), with no performance degradation after testing.
15. Packaging and Delivery
    • Operation Details: Pack qualified products in anti - static bags, place desiccants (moisture content ≤ 20%) in each bag. Stack 4 - layer boards for packaging (height ≤ 10cm), and use layered trays for 10 - layer boards to avoid extrusion deformation. Attach a test report when delivering, including electrical performance data and reliability test results to ensure traceability.

II. Core Quality Management System (QMS) for 4 - 10 - layer PCBs

1. Incoming Quality Control (IQC): Controlling Material Quality at the Source
   • Base - material Testing: Randomly inspect 5 sheets per batch. Test Tg (by Differential Scanning Calorimetry DSC), dielectric constant (by impedance analyzer), and water absorption rate (by 120℃ baking weight - loss method). Reject the entire batch if it is unqualified.
   • Copper Foil/Prepreg Testing: Test the roughness (Ra≤0.8μm) and tensile strength (≥300MPa) of the copper foil, and test the resin content (error ±2%) and resin - flow amount (20 - 30%) of the prepreg to ensure they match the base material.
2. In - process Quality Control (IPQC): Real - time Monitoring of Key Processes
   • Inner - layer Etching: Randomly inspect 1 board every 30 minutes. Measure the line - width with a microscope (deviation ≤ ±3μm), and test the etchant concentration once an hour (copper chloride concentration of 180±5g/L).
   • Lamination Process: Monitor the temperature (±3℃), pressure (±1kg/cm²), and vacuum degree (≤10mbar) in real - time. After laminating the first piece, conduct 金相切片 (metallographic sectioning) to confirm no bubbles between layers (bubbles with a diameter ≤ 50μm are unqualified).
   • Via Metallization: Test the hole resistance (≤50mΩ) every hour after copper - plating, and test the hole - copper thickness (20 - 25μm) after electro - plating. Adjust the plating solution parameters immediately if the values exceed the tolerance.
3. Final Quality Control/Final Quality Inspection (FQC/OQC): Verifying All Items for Qualified Delivery
   • FQC Full - inspection: Inspect the appearance (no bubbles or exposed copper in the solder - mask layer, no oxidation on the pads) and dimensions (shape error ≤ ±0.1mm) at 100%. The sampling inspection ratio for electrical performance should be ≥10%.
   • OQC Sampling Inspection: Randomly inspect 3% of each batch for reliability testing (temperature cycling, damp - heat), and check the consistency between the test report and the product to ensure no mis - dispatch or missed inspection.
4. Abnormality Control: Closing - loop Handling of Quality Issues
   • Abnormality Response: If non - conformity (such as inner - layer short - circuit) is found during the process, stop the machine immediately. The QE (Quality Engineer) analyzes the cause (such as deviation in exposure parameters, etchant contamination) and formulates corrective measures (adjust exposure energy, replace the etchant).
   • Traceability System: Assign a unique SN code to each board, record the base - material batch, process parameters, and test results. If quality problems occur later, it can be traced back to the specific process and responsible person to avoid batch accidents.

III. Differential Adaptation of Manufacturing and Control for 4 - 10 - layer PCBs